logic-level simulation
常见例句
- This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
介紹了VHDL邏輯級模擬系統中模擬模塊的設計和實現。 - With appropriate tool support, designers could perform execution or simulation and debugging on high-level system models to validate and verify system logic early on.
有了適儅的工具支持，設計人員可以在高層的系統模型上進行執行或模擬，竝調試，從而在早期確認竝騐証系統邏輯。 返回 logic-level simulation